This invention relates generally to semiconductor chip package assembly, and in particular to wire bonding package assembly. More specifically, the invention relates to lead frame packages with expansion planes and corresponding methods for their assembly.
In order for a semiconductor chip (also referred to as a “die”) to operate, power must be supplied through a power delivery system. Some power delivery systems are configured to include an intermediary connection (e.g., power or ground) integral to the semiconductor chip package, which houses the semiconductor chip. This intermediary connection allows for the distribution of power to or from the semiconductor chip, thereby, facilitating in the operation of the semiconductor chip.
A commonly used intermediary connection is an interposer ring (IR). An interposer ring is often integrated with a lead frame semiconductor package, such as a plastic quad flatpack (PQFP) or a thin quad flatpack (TQFP) semiconductor chip package. A typical interposer ring is composed of a flat sheet of conductive material with a sufficiently sized opening in the middle to house a semiconductor chip. The semiconductor chip is typically centered within the interposer ring opening on a die attach pad, which is used to support the semiconductor chip that sit on it. Since the interposer ring surrounds the semiconductor chip and is further insulated from the die attach pad with an electrical insulator, a wire bond connection for distributing power can be made between the semiconductor chip and the interposer ring. As such, the interposer ring serves as a power ring.
Although the interposer ring provides a good intermediary connection, improvements can still be made. The design of the intermediary connection may have a substantial impact on the performance of the semiconductor chip. In particular, the performance of the semiconductor chip can be substantially affected by electrical parasitics (e.g., inductance) introduced by the intermediary connection into the semiconductor chip's power delivery system. If not controlled, electrical parasitics may adversely affect the performance of the semiconductor chip.
Accordingly, there is a need to provide improved semiconductor chip packages and corresponding packaging methods that can minimize electrical parasitics introduced into the semiconductor chip's electrical system (e.g., power delivery system, signal loops, etc.), thereby, improving the semiconductor chip's performance.